Introduction to the Introduction

So during the fall semester 2015, I took an FPGA design class as a technical elective at university. I discovered through the various projects and assignments that I really enjoyed working with FPGAs and addressing the challenges that come with programming logic and thinking in parallel. So to continue this path, I planned out a semester of independent study during spring 2016 where I work on a project where I design my own microprocessor from scratch on an FPGA. The architecture is based on the classic MOS 6502 and so the project was born.

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Sixty-five-oh-who?

It’s an 8-bit microprocessor first introduced way back in 1975 by MOS Technology and revolutionized the home computer and game console industry throughout the 80’s. It was the brains of landmark systems such as the Atari, Apple II, Nintendo NES, and Commodore 64. It has only 3 registers (A, X, and Y) and a stack pointer. Here’s how the assembly language looks like:


LDA #$c0  ;Load the hex value $c0 into the A register
TAX       ;Transfer the value in the A register to X
INX       ;Increment the value in the X register
ADC #$c4  ;Add the hex value $c4 to the A register
BRK       ;Break - we're done

The fact that it’s so simple and so ubiquitous makes this a perfect target to learn about computer architectures and implementing them on an FPGA. Though it was way before my time, a lot of people grew up with this chip and with the invention of the internet we started seeing countless projects dedicated to documenting this chip from the block diagram all the way to the silicon transistor level and simulating this countless times in software as well as in hardware and FPGA logic. With all the documentation available on this chip,

The Project

There are already cycle-accurate implementations of the 6502 on FPGA logic. This project does not aim to supersede those projects. Here are the goals of this project:

  • Design and test microprocessor design based on the documented MOS 6502 instructions.
  • Instructions will operate according to the documented behavior but won’t necessarily be implemented in the same way the original instructions were implemented.
  • Simplicity, directness, and understandability of the Verilog code will be take precedence over raw performance
  • Will not be cycle-accurate. Instructions won’t be delayed unless there is a particular timing issue.
  • Instructions may be modified or expanded as the project grows.
  • Educating myself and others interested in FPGA design in Verilog as well as the workings of the 6502.

Timeline

The project will be broken into five parts:

  1. The Arithmetic Logic Unit (ALU)
  2. Arithmetic instructions
  3. Stack-based, memory-based, and other instructions
  4. Peripheral and processor integration with memory-mapped I/O
  5. Demo using short assembly program

All of these will be completed and uploaded throughout spring 2016.

I hope that my project will be of use to anyone who wants to sharpen their Verilog skills and who wants to understand more about how CPUs work. Stay tuned for updates!